With recent miniaturization and high performance of electronic devices, printed wiring boards are required to have higher wiring density and higher integration and to have a thinner board.
As a package structure based on these requirements, for example, Patent Literature 1 and Patent Literature 2 propose a coreless substrate which does not have a core substrate and mainly includes a build-up layer capable of high-density wiring. The coreless substrate is obtained by forming a build-up layer on a support (core substrate) such as a metal plate and then removing the support (core substrate), that is, in this case, only the build-up layer. As the build-up layer used for forming the coreless substrate, a prepreg obtained by impregnating a glass cloth with a resin composition, an insulating resin containing no glass cloth, or the like is used.
Since the rigidity of the coreless substrate is lowered due to thinning caused by removing the support (core substrate), the case that the semiconductor package warps when the semiconductor element is mounted and packaged becomes more conspicuous. The warpage is considered to be one of the factors that cause connection failure between the semiconductor element and the printed wiring board, and in the coreless substrate, a more effective reduction of the warpage is demanded.
One of the factors that warp the semiconductor package is the difference in the coefficient of thermal expansion between the semiconductor element and the printed wiring board. Generally, since the coefficient of thermal expansion of the printed wiring board is larger than the coefficient of thermal expansion of the semiconductor element, stress is generated by the thermal history or the like applied at the time of mounting the semiconductor element, and warpage occurs. Therefore, in order to suppress warpage of the semiconductor package, it is necessary to reduce the coefficient of thermal expansion of the printed wiring board to reduce the difference from the coefficient of thermal expansion of the semiconductor element, which is also applicable to the coreless substrate. Therefore, the build-up layer used for the coreless substrate is required to have a low thermal expansion coefficient.
Patent Literature 3 discloses a method of laminating an insulating resin containing no glass cloth as an insulating layer on both sides of a prepreg, but this method tends to increase warpage because the coefficient of thermal expansion increases.
Here, it is generally known that the coefficient of thermal expansion of a prepreg obtained by impregnating a glass cloth with a resin composition follows the Scapery Equation represented by the following formula.A≈(ArErFr+AgEgFg)/(ErFr+EgFg)(In the formula, A represents a coefficient of thermal expansion of the prepreg, Ar represents a coefficient of thermal expansion of the resin composition, Er represents an elastic modulus of the resin composition, Fr represents a volume fraction of the resin composition, Ag represents a coefficient of thermal expansion of the glass cloth, Eg represents an elastic modulus of the glass cloth, and Fg represents a volume fraction of the glass cloth.)
From the above Scapery Equation, it can be seen that when a glass cloth having the same physical property is used at a given volume fraction, the low thermal expansion of the prepreg can be achieved by reducing the elastic modulus and the coefficient of thermal expansion of the resin composition.
For example, Patent Literature 4 discloses a prepreg formed of a resin composition containing a specific low elasticity component and a woven fabric base material as a prepreg capable of reducing warpage of a semiconductor package.